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UPD6708 Datasheet(PDF) 22 Page - Renesas Technology Corp |
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UPD6708 Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 74 page  20 µPD6708 3. INTERNAL CONFIGURATION The µPD6708 is composed of the following four blocks. (1) Data link layer controller (2) Physical layer controller (3) IEBus driver/receiver (4) Host interface Figure 3-1. µPD6708 Internal Blocks Data Link Layer Controller Receiver Driver IEBus Driver/Receiver Filter Bit Sequencer Physical Layer Controller Host Interface Status Register (STR) Read Data Buffer (RDB) 20 Bytes Write Data Buffer (WDB) 4 Bytes Command Register (CMR) Shift Register Serial I/O Controller BUS+ BUS– SCK SO SI CS IRQ C/D R/W |
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