DSP56800 datasheet(2/44 Pages) MOTOROLA

2 / 44 page

DSP56F826 Preliminary Technical Data

Part 1 Overview

1.1 DSP56F826 Features

1.1.1

Digital Signal Processing Core

•

Efficient 16-bit DSP56800 Family DSP engine with dual Harvard architecture

•

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

•

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

•

Two 36-bit accumulators, including extension bits

•

16-bit bidirectional barrel shifter

•

Parallel instruction set with unique DSP addressing modes

•

Hardware DO and REP loops

•

Three internal address buses and one external address bus

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Four internal data buses and one external data bus

•

Instruction set supports both DSP and controller functions

•

Controller style addressing modes and instructions for compact code

•

Efficient C Compiler and local variable support

•

Software subroutine and interrupt stack with depth limited only by memory

•

JTAG/OnCE Debug Programming Interface

1.1.2

Memory

•

Harvard architecture permits as many as three simultaneous accesses to program and data memory

•

On-chip memory including a low cost, high volume flash solution

—31.5K

× 16-bit words of Program Flash

—512

× 16-bit words of Program RAM

—2K

× 16-bit words of Data Flash

—4K

× 16-bit words of Data RAM

—2K

× 16-bit words of BootFLASH

•

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64 K

× 16-bit data memory

— As much as 64 K

× 16-bit program memory

1.1.3

Peripheral Circuits for DSP56F826

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One General Purpose Quad Timer totalling 7pins

•

One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)

•

One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling

4 pins

•

Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)

DSP56800 Datasheet(PDF) 2 Page - Motorola, Inc

DSP56800 Datasheet(HTML) 2 Page - Motorola, Inc

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