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UPD17062 Datasheet(PDF) 130 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 130 Page - Renesas Technology Corp |
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130 / 298 page  128 µPD17062 MAIN A MAIN B A C B A MAIN B A A A RETI RETI RET A A A A BANK0 CLR1 IXE DI BANK0 CLR1 IXE EI Undefined Undefined Main routine Interrupt A Interrupt B Interrupt C Undefined Fig. 11-8 Example of Using Multiple Level-3 Interrupts To interrupt A, be sure to set a lower priority than interrupts B and C. Fix the bank register and index enable flag (BANK0 and IXE = 0 in this example) in the main routine that permits interrupt A. This processing enables the use of RET instructions for multiple interrupts of three levels after specifying the bank register and index enable flag of the main routine. If the bank register and index enable flag at interrupt A are exactly the same as those of the main routine, the RETI instruction can be used. However, because the operation of the 17K series emulator differs as shown in Fig. 11-9, the RETI instruction cannot be used for debugging. |
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