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UPD17062 Datasheet(PDF) 161 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 161 Page - Renesas Technology Corp |
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161 / 298 page  159 µPD17062 (2) Cautions in using the P0D0/ADC2 to P0D3/ADC5 pins for an A/D converter P0D3/ADC5 P0D2/ADC4 P0D1/ADC3 P0D0/ADC2 A/D input A/D input Latch General-purpose port If one of the P0D0/ADC2 to P0D3/ADC5 pins is selected for an A/D converter (only one pin can be selected at one time), it is disconnected from the input latch and connected to the internal A/D converter input. If a pin happens to be at a high level when it is selected for an A/D converter, the latch circuit is held at a high. If the HALT 0001B instruction is executed under the above condition, the halt state is released immediately because the input latch is at a high. To solve the above problem, specify the input port so that a low level is input to the A/D converter, before executing the HALT 0001B instruction. |
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