AD8112 datasheet(19/28 Pages) AD

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AD8112

Rev. 0 | Page 19 of 28

APPLICATION NOTES

The AD8112 has two options for changing the programming

of the crosspoint matrix. In the first option, a serial word of 80

bits is provided to update the entire matrix. The serial data needs

to be prefixed with 40 zeros because there are 40 unconnected

bits. The second option allows for changing a single output’s

programming via a parallel interface. The serial option requires

fewer signals but more time (clock cycles) for changing the pro-

gramming, whereas the parallel programming technique

requires more signals but can change outputs individually

and requires fewer clock cycles to complete programming.

SERIAL PROGRAMMING

The serial programming mode uses the device pins: CE, CLK,

DATA IN, UPDATE, and SER/PAR. The first step is to assert

a low on SER/PAR to enable the serial programming mode. The

CE pin for the chip must be low to allow data to be clocked into

the device. The CE signal can be used to address an individual

device when devices are connected in parallel.

The UPDATE signal should be high during the time that data is

shifted into the device’s serial port. Although the data shifts in

when UPDATE is low, the transparent asynchronous latches allow

the shifting data to reach the matrix. This causes the matrix to

try to update to every intermediate state as defined by the

shifting data.

The data at DATA IN is clocked in upon each falling edge of

CLK. A total of 80 bits must be shifted in to complete the pro-

gramming because there are 40 unconnected bits. For each of

the eight outputs, there are four bits (D0 to D3) that determine

the source of the input followed by one bit (D4) that determines

the enabled state of the output. If D4 is low (output disabled),

the four associated bits (D0 to D3) do not matter, because no

input will be switched to that output.

The most significant output address data is shifted in first, and

then followed in sequence until the least significant output address

data is shifted in. At this point UPDATE can be taken low, which

programs the device with the data that was just shifted in. The

UPDATE registers are asynchronous, and when UPDATE is low

(and CE is low), they are transparent.

If more than one AD8112 device is to be serially programmed

in a system, the DATA OUT signal from one device can be con-

nected to the DATA IN of the next device to form a serial chain.

All of the CLK, CE, UPDATE, and SER/PAR pins should be

connected in parallel and operated as described previously. The

serial data is input into the DATA IN pin of the first device

of the chain, and it ripples through to the last device. There-

fore, the data for the last device in the chain should come at the

beginning of the programming sequence. The length of the

programming sequence is 80 bits times the number of devices

in the chain.

PARALLEL PROGRAMMING

When using the parallel programming mode, it is not necessary

to reprogram the entire device when making changes to the

matrix. In fact, parallel programming allows the modification

of a single output. Because this requires only one CLK/UPDATE

cycle, significant time is saved by using parallel programming.

One important consideration when using parallel programming

is that the RESET signal does not reset all registers in the AD8112.

When taken low, the RESET signal only sets each output to the

disabled state. This is helpful during power-up to ensure that

two parallel outputs will not be active at the same time.

After initial power-up, the internal registers in the device gener-

ally have random data, even though the RESET signal has been

asserted. If parallel programming is used to program one output,

then that output is properly programmed, but the rest of the

device has a random program state depending on the internal

programming, it is essential that all outputs be programmed to

a desired state after power-up to ensure that the programming

matrix is always in a known state. Then, parallel programming

can be used to modify a single output or multiple outputs.

Similarly, if both CE and UPDATE are taken low after initial

power-up, the random power-up data in the shift register is

programmed into the matrix. Therefore, to prevent the crosspoint

from being programmed into an unknown state, do not apply

low logic levels to both CE and UPDATE after power is initially

applied. Programming the full shift register one time to a desired

state, by either serial or parallel programming after initial

power-up, eliminates the possibility of programming the matrix

to an unknown state.

To change an output programming via parallel programming,

SER/PAR and UPDATE should be taken high and CE should be

taken low. The CLK signal should be in the high state. The 3-bit

address of the output to be programmed should be put on A0 to

A2. The first four data bits (D0 to D3) should contain the infor-

mation identifying the input that is programmed to the addressed

output. The fifth data bit (D4) determines the enabled state of

the output. If D4 is low (output disabled), the data on D0 to D3

does not matter.

After the desired address and data signals have been established,

the data can be latched into the shift register by a high to low

transition of the CLK signal. The matrix will not be programmed,

however, until the UPDATE signal is taken low. It is therefore

possible to latch in new data for several or all outputs via suc-

cessive negative transitions of CLK while UPDATE is held high,

and then for the new data to take effect when UPDATE goes

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