NJ8821

mA

mA

V

V

V

V

V

V

µA

V

V

V

V

V

V

TTL compatible

See note 1

5·5

1·5

0·4

0·4

7

0·4

±0·1

0·4

0·75

0·75

Supply current

OUTPUT LEVELS

Modulus Control Output (MC)

High level

Low level

Lock Detect Output (LD)

Low level

Open drain pull-up voltage

PDB Output

High level

Low level

3-state leakage current

INPUT LEVELS

Data Inputs (D0-D3)

High level

Low level

Program Enable Input (PE)

High level

Low level

Data Select Inputs (DS0-DS2)

High level

Low level

4·6

4·6

4·25

4·25

4·25

2

Test conditions unless otherwise stated:

DC Characteristics

Value

Typ.

Max.

Characteristic

Min.

3·5

0·7

Units

Conditions

0 to 5V

square

wave

mVRMS

MHz

ns

µs

µs

µs

µs

µs

ns

k

Ω

nF

k

Ω

V/Rad

50

1

5

Propagation delay, clock to MC

Digital phase detector propagation delay

Gain programming resistor, RB

Hold capacitor, CH

Output resistance, PDA

Digital phase detector gain

30

500

0·4

AC Characteristics

Value

Typ.

Max.

Characteristic

Min.

Units

Conditions

200

10·6

2

1

1

1

1

5

10MHz AC-coupled sinewave

See note 4.

See note 2.

See Fig. 6

See note 3.

NOTES

1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.

2. All counters have outputs directly synchronous with their respective clock rising edges.

3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant

to the loop. An external 1nF hold capacitor will give a maximum time constant of 5

µs, typically.

4. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.