NJ8821

PIN DESCRIPTIONS

Name

Description

Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Output at

by gain (programmed by RB).

Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.

An open-drain lock detect output at low level when phase error is within PDA window (in lock); high

impedance at all other times.

The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when

a full logic swing is available, may be DC-coupled.

Negative supply (ground).

Positive supply.

These pins form an on-chip reference oscillator when a series resonant crystal is connected across

them. Capacitors of appropriate value are also required between each end of the crystal and ground

to provide the necessary additional phase shift. An external reference signal may, alternatively, be

applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may

be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being

twice the programmed number.

Data on these inputs is transferred to the internal data latches during the appropriate data read time

slot. D3 is MSB, D0 is LSB.

No connection

This pin is used as a strobe for the data. A logic ‘1’ on this pin transfers data from the D0-D3 pins to

the internal latch addressed by the data select (DS0-DS2) pins . A logic ‘0’ disables the data inputs.

Data select inputs for addressing the internal data latches

Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning

of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and

remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.

This gives a total division ratio of

MP1A, where P and P11 represent the dual-modulus prescaler

values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a

division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023

and, for correct operation,

M>A. Where every possible channel is required, the minimum total division

ratio should be

An external sample and hold phase comparator gain programming resistor should be connected

PDA

PDB

LD

OSC IN/

OSC OUT

D0-D3

NC

PE

DS0-DS2

MC

RB

CH

3

Pin no.

1

2

3

4

5

6

7, 8

9,10, 11, 12

13

14

15, 16, 17

18

19

20

Fig. 3 Typical supply current v. input frequency

Fig. 4 Typical supply current v. input level, OSC IN

OSC IN

INPUT FREQUENCY (MHz)

1

2

3

4

5

6

7

8

9

10

2·0

1·5

1·0

0·5

TOTAL SUPPLY CURRENT IS

AND OSC IN

INPUT LEVEL (V RMS)

0·2

0·4

0·6

0·8

1·0

1·2

1·4

1·6

8

7

6

5

4

3

2

1

0V TO 5V SQUARE WAVE

10MHz

1MHz