+3V Voltage Monitoring, Low-Cost µP

Supervisory Circuits

8

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WDO can be connected to the nonmaskable interrupt

threshold, WDO immediately goes low, even if the

watchdog timer has not timed out (Figure 3). Normally,

this would trigger an NMI, but since reset is asserted

simultaneously, the NMI is overridden. The WDO

should not be connected to RESET directly. Instead,

connect WDO to MR to generate a reset pulse when it

times out.

Manual Reset

The manual reset (MR) input allows RESET and RESET

to be activated by a pushbutton switch. The switch is

effectively debounced by the 140ms minimum reset

pulse width. MR can be driven by an external logic line

since it is TTL/CMOS compatible. The minimum MR

Power-Fail Comparator

The power-fail comparator can be used for various pur-

poses because its output and noninverting input are

not internally connected. The inverting input is internally

connected to a 1.25V reference. The power-fail com-

parator has 10mV of hysteresis, which prevents repeat-

ed triggering of the power-fail output (PFO).

+3.3V

0V

+3.3V

+1V

0V

RESET

RESET

WDO*

+3.3V

0V

MR*

*NOTE: MR EXTERNALLY DRIVEN LOW.

WDO TIMING SHOWN FOR MAX706P/R/S/T.

+3.3V

0V

+3V/+3.3V

0V

WDI

+3V/+3.3V

0V

WDO

+3V/+3.3V

0V

RESET

RESET EXTERNALLY

TRIGGERED BY MR

MAX706_

MAX708R/S/T

RESET

(RESET)

130kΩ

1%

PARAMETER

MIN

TYP

MAX

UNIT

+12V RESET

THRESHOLD AT +25°C

10.24

10.87

11.50

V

1MΩ

1%

+3V/+3.3V

+12V

PFI

( ) ARE FOR MAX706P/AP

GND

MR

PFO

TO µP

MAX706R/S/T

MAX708R/S/T

MAX706AR/AS/AT

RESET

R1

Figure 4. MAX706AP/AR/AS/AT Watchdog Timing

Figure 3. RESET, RESET, MR, and WDO Timing

Figure 5. Monitoring Both +3V/+3.3V and +12V

Figure 6. RESET Valid to GND Circuit