UPD75004 datasheet(13/68 Pages) RENESAS

13 / 68 page

µPD75004, 75006, 75008

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0-KR3

KR4-KR7

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60-P63

P70-P73

Input

B -C

E-B

F -A

F -B

M -C

B -C

F -A

Pin Name Input/Output

Also Served

Functon

When Reset

Input/

Output

Circuit

TYPE*1

3.2

NON PORT PINS

Timer/event counter external event pulse Input

Timer/event counter output

Clock output

Fixed frequency output (for buzzer or for trim-

ming the system clock)

Serial clock input/output

Serial data output

Serial bus input/output

Serial data input

Serial bus input/output

Edge detection vector interrupt input (both

rising and falling edge detection are effective)

Edge detection vector

interrupt input (detection

edge can be selected)

Edge detection testable

input (rising edge detection)

Clock synchronous

Asynchronous

X1, X2

RESET

NC *2

VDD

VSS

Input

—

Input

—

Input

—

*1: Circles indicate Schmitt trigger inputs.

2: When sharing the printed circut board with the

µPD75P008, the NC pin must be directly

connected to VDD.

Input

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

XT1

XT2

—

Input

—

Input

—

Parallel falling edge detection testable input

To connect the crystal/ceramic oscillator to the

main system clock generator. When inputting the

external clock, input the external clock to pin X1,

and the reverse phase of the external clock to pin

X2.

To connect the crystal oscillator to the subsystem

clock generator.

When the external clock is used, pin XT1 inputs

the external clock. In this case, pin XT2 must be

left open.

System reset input

No connection

Positive power supply

GND

UPD75004 Datasheet(PDF) 13 Page - Renesas Technology Corp

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