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12F683 Datasheet(PDF) 70 Page - Microchip Technology

Part # 12F683
Description  8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
PDF  148 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

12F683 Datasheet(HTML) 70 Page - Microchip Technology

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PIC12F683
DS41211B-page 68
Preliminary
 2004 Microchip Technology Inc.
10.5
Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(64 ms
duration)
prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
10.6
Data EEPROM Operation During
Code-Protect
Data memory can be code-protected by programming
the CPD bit in the Configuration Word (Register 12-1)
to ‘0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which
outputs
the
contents
of
data
memory.
Programming unused locations in program memory to
‘0’ will also help prevent data memory code protection
from becoming breached.
TABLE 10-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 0000
0Ch
PIR1
EEIF
ADIF
CCP1IF
—
CMIF
OSFIF
TMR2IF TMR1IF 000- 0000 000- 0000
8Ch
PIE1
EEIE
ADIE
CCP1IE
—
CMIE
OSFIE
TMR2IE TMR1IE 000- 0000 000- 0000
9Ah
EEDAT
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
9Bh
EEADR
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
9Ch
EECON1
—
—
—
—
WRERR
WREN
WR
RD
---- x000 ---- q000
9Dh
EECON2(1) EEPROM Control Register 2
---- ---- ---- ----
Legend:
x
= unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
Note
1:
EECON2 is not a physical register.



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