UPD98405 datasheet(21/68 Pages) RENESAS

21 / 68 page

Data Sheet S12689EJ3V0DS

µµµµPD98405

1.2.2 PCI bus interface signal (PCI_MODE pin: high level)

The

µPD98405 has a 32-/64-bit PCI bus interface. This bus interface can be directly connected to a PCI bus. In

addition, the

µPD98405 also has a serial EEPROM interface and an expansion ROM interface.

<1>

PCI bus interface signals

(1/2)

Pin No.

Pin Name

QFP

FBGA

I/O

Level

Function

AD31 to AD0

295 to 297,

300 to 303,

3, 6, 9 to 12,

15 to 17,

34 to 36,

39 to 42,

45, 47, 48,

51 to 54,

57 to 58

E6, A4, B5,

B4, A3, D4,

B3, B1, E5,

D1, F5, F4,

G5, F1, G6,

G4, K6, L5,

L2, M4, M1,

M2, M5,

N1, N4, P6,

P2, P4, R1,

R2, R5, T1

I/O

3-state

PCI

Address/data.

AD31 to AD0 constitute a 32-bit multiplexed address/data

bus. When the

µPD98405 operates as a bus master, it

drives an address at the first clock and transfers data at the

second clock and onward.

PCBE3_B

PCBE2_B

PCBE1_B

PCBE0_B

I/O

3-state

PCI

Bus command/byte enable.

These signals define a “bus command” (bus transaction that

occurs) in the address phase. In the data phase, they

indicate which byte lane holds valid data. The PCBE3_B pin

corresponds to byte 3 (bits 31 to 24), and PCBE0_B pin

corresponds to byte 0 (bits 7 to 0).

PAR

I/O

3-state

PCI

Parity.

This signal indicates an even parity on the AD31 to AD0 and

PCBE3_B to PCBE0_B pins, including the PAR signal.

When the

µPD98405 is operating as a master, the PAR

signal becomes active in the address and write data phases.

When the

µPD98405 is operating as a target, this signal

becomes active in the read data phase.

FRAME_B

I/O

Sustained

3-state

PCI

Frame.

This signal indicates the start and period of a bus

transaction. When this signal is asserted active, it indicates

the start of a bus transaction. While it is active, data is

transferred. It is deasserted inactive when the next data

transfer phase will transfer last data of the transaction.

TRDY_B

I/O

Sustained

3-state

PCI

Target ready.

This signal goes low when the target device is ready to

complete the transaction of the current data. This signal is

used in combination with IRDY_B, and read/write data

transfer is executed when both IRDY_B and TRDY_B

signals are low.

IRDY_B

I/O

Sustained

3-state

PCI

Initiator ready.

This signal goes low when the initiator is ready to complete

the transaction of the current data. This signal is used in

combination with TRDY_B, and read/write data transfer is

executed when both IRDY_B and TRDY_B are low.

If FRAME_B and IRDY_B are both inactive, the bus cycle is

not executed. A wait cycle is inserted until both IRDY_B and

TRDY_B are asserted active.

UPD98405 Datasheet(PDF) 21 Page - Renesas Technology Corp

UPD98405 Datasheet(HTML) 21 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL