AD8021 datasheet(23/32 Pages) AD

23 / 32 page

AD7952

Rev. 0 | Page 23 of 32

Power Down

OVDD should be set to the same level as the system interface.

Sufficient decoupling is required, consisting of at least a 10 μF

capacitor and a 100 nF capacitor with the 100 nF capacitors

placed as close as possible to the AD7952.

Setting PD = high powers down the AD7952, thus reducing

supply currents to their minimums, as shown in Figure 23. When

the ADC is in power-down, the current conversion (if any) is

completed and the digital bus remains active. To further reduce

the digital supply currents, drive the inputs to OVDD or OGND.

Power Sequencing

The AD7952 is independent of power supply sequencing and is

very insensitive to power supply variations on AVDD over a wide

frequency range, as shown in Figure 32.

Power-down can also be programmed with the configuration

that when using the configuration register, the PD input is a

don’t care and should be tied to either high or low.

10000

FREQUENCY (kHz)

100

1000

EXT REF

INT REF

CONVERSION CONTROL

The AD7952 is controlled by the CNVST input. A falling edge

on CNVST is all that is necessary to initiate a conversion. A

detailed timing diagram of the conversion process is shown in

Figure 34. Once initiated, it cannot be restarted or aborted,

even by the power-down input, PD, until the conversion is

completed. The CNVST signal operates independently of the CS

and RD signals.

BUSY

MODE

CONVERT

ACQUIRE

CONVERT

CNVST

Figure 32. AVDD PSRR vs. Frequency

Power Dissipation vs. Throughput

In impulse mode, the AD7952 automatically reduces its power

consumption at the end of each conversion phase. During the

acquisition phase, the operating currents are very low, which allows

a significant power savings when the conversion rate is reduced

(see Figure 33). This feature makes the AD7952 ideal for very

low power, battery-operated applications.

Figure 34. Basic Conversion Timing

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot, undershoot, or ringing.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital supply

currents even further, drive the digital inputs close to the power

rails (that is, OVDD and OGND).

The CNVST trace should be shielded with ground, and a low value

(such as 50 Ω) serial resistor termination should be added close

to the output of the component that drives this line.

1000

1000000

100

1000

10000

100000

PDREF = PDBUF = HIGH

WARP MODE POWER

IMPULSE MODE POWER

For applications where SNR is critical, the CNVST signal should

have very low jitter. This can be achieved by using a dedicated

oscillator for CNVST generation, or by clocking CNVST with a

high frequency, low jitter clock, as shown in Figure 27.

Figure 33. Power Dissipation vs. Sample Rate

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