AD8021 datasheet(27/32 Pages) AD

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AD7952

Rev. 0 | Page 27 of 32

SLAVE SERIAL INTERFACE

The pins multiplexed on D[19:2] used for slave serial

interface are: EXT/INT, INVSCLK, SDIN, SDOUT,

SDCLK, and RDERROR.

External Clock (SER/PAR = High, EXT/INT = High)

Setting the EXT/INT = high allows the AD7952 to accept an

externally supplied serial data clock on the SDCLK pin. In this

mode, several methods can be used to read the data. The

external serial clock is gated by CS. When CS and RD are both

low, the data can be read after each conversion or during the

following conversion. A clock can be either normally high or

normally low when inactive. For detailed timing diagrams,

see Figure 43 and Figure 44.

While the AD7952 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins

or degradation of the conversion result may occur. This is

particularly important during the last 450 ns of the conversion

phase because the AD7952 provides error correction circuitry

that can correct for an improper bit decision made during the

first part of the conversion phase. For this reason, it is recom-

mended that any external clock provided is a discontinuous

clock that transitions only when BUSY is low or, more importantly,

that it does not transition during the last 450 ns of BUSY high.

External Discontinuous Clock Data Read After

Conversion

Though the maximum throughput cannot be achieved using

this mode, it is the most recommended of the serial slave modes.

Figure 43 shows the detailed timing diagrams for this method.

After a conversion is complete, indicated by BUSY returning low,

the conversion result can be read while both CS and RD are low.

Data is shifted out MSB first with 14 clock pulses and, depending

on the SDCLK frequency, can be valid on the falling and rising

edges of the clock.

One advantage of this method is that conversion performance is

not degraded because there are no voltage transients on the digital

interface during the conversion process. Another advantage is

the ability to read the data at any speed up to 40 MHz, which

accommodates both the slow digital host interface and the fastest

serial reading.

Daisy-Chain Feature

Also in the read after convert mode, the AD7952 provides a

daisy-chain feature for cascading multiple converters together

using the serial data input pin, SDIN. This feature is useful for

reducing component count and wiring connections when

desired, for instance, in isolated multiconverter applications.

See Figure 43 for the timing details.

An example of the concatenation of two devices is shown in

Figure 42.

Simultaneous sampling is possible by using a common CNVST

signal. Note that the SDIN input is latched on the opposite edge

of SDCLK used to shift out the data on SDOUT (SDCLK

falling edge when INVSCLK = low). Therefore, the MSB

of the upstream converter follows the LSB of the downstream

converter on the next SDCLK cycle. In this mode, the 40 MHz

SDCLK rate cannot be used because the SDIN-to-SDCLK setup

time, t33, is less than the minimum time specified. (SDCLK-

to-SDOUT delay, t32, is the same for all converters when

simultaneously sampled). For proper operation, the SDCLK

edge for latching SDIN (or ½ period of SDCLK) needs to be

SDCLK

or the maximum SDCLK frequency needs to be

)

(

SDCLK

If not using the daisy-chain feature, the SDIN input should

always be tied either high or low.

SDCLK

SDOUT

RDC/SDIN

AD7952

(DOWNSTREAM)

AD7952

(UPSTREAM)

BUSY

OUT

BUSY

DATA

OUT

SDCLK

RDC/SDIN

SDOUT

SDCLK IN

CNVST IN

CNVST

CS IN

Figure 42. Two AD7952 Devices in a Daisy-Chain Configuration

External Clock Data Read During Previous Conversion

Figure 44 shows the detailed timing diagrams for this method.

During a conversion, while both CS and RD are low, the result

of the previous conversion can be read. The data is shifted out,

MSB first, with 14 clock pulses, and depending on the SDCLK

frequency, can be valid on both the falling and rising edges

of the clock. The 14 bits have to be read before the current

conversion is completed; otherwise, RDERROR is pulsed high

and can be used to interrupt the host interface to prevent

incomplete data reading.

To reduce performance degradation due to digital activity,

a fast discontinuous clock of at least 40 MHz is recommended to

ensure that all the bits are read during the first half of the SAR

conversion phase.

The daisy-chain feature should not be used in this mode because

digital activity occurs during the second half of the SAR

conversion phase, likely resulting in performance degradation.

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