TAS5036AIPFC datasheet(13/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

Architecture Overview

The TAS5036A is composed of six functional elements:

•

Clock, PLL, and serial data interface (I2S)

•

Reset/power-down circuitry

•

Serial control interface (I2C)

•

Signal processing unit

•

Pulse width modulator (PWM)

•

Power supply

2.1

Clock and Serial Data Interface

The TAS5036A clock and serial data interface contain an input serial data slave and the clock master/slave

interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF

receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The

serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates

of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz. The serial data interfaces support left

justified and right justified for 16, 20, and 24 bits. In addition, the serial data interface supports the DSP protocol

for 16 bits and the I2S protocol for 24 bits.

The TAS5036A can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),

and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The

TAS5036A is a clock master when it generates these clocks and is a clock slave when it receives these clocks.

The TAS5036A is a synchronous design that relies upon the master clock to provide a reference clock for all

of the device operations and communication via the I2C. When operating as a slave, this reference clock is

MCLK_IN. When operating as a master, the reference clock is either a TTL clock input to XTAL_IN or a crystal

attached across XTAL_IN and XTAL_OUT.

The clock and serial data interface has two control parameters, data sample rate and clock master or slave.

2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection

The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (0x02). The data

sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output

frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double

speed, and quad speed.

Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the

master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz.

Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates

of 176.4 kHz and 192 kHz.

The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits

in the system control register 0 (0x02) through the serial control interface. The PWM is placed in double speed

mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register.

Quad-speed mode is supported. In slave mode it is auto detected, and in master mode it is invoked using the

I2C serial control interface. In slave mode, if the TAS5036A is not in double speed mode, quad-speed mode

is automatically detected when MCLK_IN is 128Fs. In master mode, the PWM is placed in quad-speed mode

by setting the quad-speed bit in the system control register through the serial control interface.

If the master clock is well behaved during the frequency transition (the high or low clock periods are not less

than 20 ns) then a simple speed selection is simply performed by setting the DBSPD terminal or the serial

control register.

When the sample rate is changed, the TAS5036A temporarily suspends processing, places the PWM outputs

in a hard mute (PWM P outputs low; PWM M outputs high and all VALID signals low), resets all internal

processes, and suspends all I2C operations. The TAS5036A then performs a partial re-initialization and

noiselessly restarts the PWM output. The TAS5036A preserves all control register settings throughout this

sequence. If desired, the sample rate change can be performed while mute is active to provide a completely

silent transition. The timing of this control sequence is shown in Section 4.

TAS5036AIPFC Datasheet(PDF) 13 Page - Texas Instruments

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