RT4823WSC datasheet(14/20 Pages) RICHTEK

14 / 20 page

RT4823

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS4823-01

September 2022

Application Information

Enable

The device can be enabled or disabled by the EN pin.

When the EN pin is higher than the threshold of

logic-high, the device starts operating with soft-start.

Once the EN pin is set at low, the device will be shut

down. In shutdown mode, the converter stops

switching, internal control circuitry is turned off, and

the load is disconnected from the input. This also

means that the output voltage can drop below the

input voltage during shutdown.

Power Frequency Modulation (PFM)

PFM is used to improve efficiency at light load. When

the output voltage is lower than a set threshold

voltage, the converter will operate in PFM. It raises

the output voltage with several pulses until the loop

exits PFM.

Thermal Shutdown

The device has a built-in temperature sensor which

monitors the internal junction temperature. If the

temperature exceeds the threshold, the device stops

operating. As soon as the IC temperature decreases

below the threshold with a hysteresis, it starts

operating again. The built-in hysteresis is designed to

avoid unstable operation at IC temperatures near the

over temperature threshold.

Inductor Selection

The primary concern of inductor selection is the

maximum loading of the application. The example is

given by the application condition and equations

below.

Application condition:

VIN = 3.6V, VOUT = 5V, IOUT = 1.3A, converter

efficiency = 90.2%, Frequency = 3.5MHz, L = 1

H.

Step 1 : To calculate input current (IIN).

OUT

2.001A

Eff



Step 2 : To calculate duty cycle of boost converter.

OUT

0.28

= −

Step 3 : To calculate peak current of inductor.

L(Peak)

0.5

2.145A

L Freq.



The recommended nominal inductance value is 1

H.

It is recommended to use inductor with dc saturation

current

 2200mA.

Input Capacitor Selection

At least an input capacitor of 4.7

F and the rate

voltage of 6.3V for DC bias is recommended to

improve transient behavior of the regulator and EMI

behavior of the total power supply circuit for SW. And

input capacitor placed as close as possible to the VIN

and GND pins of the IC is recommended.

Output Capacitor Selection

At least a 10

F capacitors is recommended to

improve VOUT ripple.

Output voltage ripple is inversely proportional to

COUT.

Output capacitor is selected according to output ripple

which is calculated as :

LOAD

RIPPLE(P P)

OUT

LOAD

OUT

RIPPLE(P P)

and

therefore :

and

−

=



 =

 −







 −







The maximum VRIPPLE occurs at minimum input

voltage and maximum output load.

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