PI6C4512

PLL Clock Multiplier

3

PS8763B

03/30/06

Symbol Description

Test Condition

Pin

Min.

Typ.

Max.

Units

Supply voltage

3

5.5

V

Supply current

No load, 20MHz crystal

`

12

30

mA

Input logic HIGH

ICLK

V

Input logic LOW

ICLK

V

Input logic HIGH

V

Input mid-level

V

Input logic LOW

0.5

V

CLK, REF

2.4

V

CLK, REF

0.4

V

Short circuit current

CLK

±70

mA

Symbol Parameter

Test Condition

Pin

Min.

Typ.

Max.

Unit

Input Frequency

Crystal

ICLK

5

30

MHz

Clock

ICLK

4

50

MHz

CLK

20

200

MHz

CLK

20

180

MHz

Output clock rise time

0.8V to 2.0V,

CLK

1

ns

Output clock fall time

2.0V to 0.8V,

CLK

1

ns

Output clock duty-cycle

CLK

45

50

55

%

CLK

40

50

60

BW

PLL bandwidth

f ≤ 150MHz

CLK

10

kHz

Period Jitter

100MHz to 200MHz

CLK

100

250

ps

Notes:

1.

The phase relationship between input and output clocks can change at power up.

Recommended Crystal Specifications

Parameter

Value

Units

Mode of Oscillation

Fundamental

AT

Frequency

5 - 30

MHz

Frequency Tolerance

±50

PPM

Temperature and Aging Stability

±50

PPM

CO/CI Ratio

240

Load Cap

18

pF

Equivalent Series Resistance

30

Ω

Recommended Crystal

Pericom recommends the Pericom 49S SMD series crystal,

which is a low cost, low profile SMD crystal packaged in a

HC-49/u short SMD package.

06-0034