MPQ9842GL datasheet(22/37 Pages) MPSIND

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MPQ9842

– 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER

MPQ9842 Rev. 1.1

www.MonolithicPower.com

7/29/2022

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

At a higher duty cycle operation condition, the

time period available to the bootstrap charging

is less, so the bootstrap capacitor may not be

charged sufficiently. In case the external circuit

does not have sufficient voltage or time to

charge the bootstrap capacitor, extra external

circuitry can be used to ensure that the

bootstrap voltage is in the normal operation

region.

Low Dropout Operation (BST Refresh)

To improve dropout, the MPQ9842 is designed

to operate at close to 100% duty cycle for as

long as the BST to SW voltage is greater than

2.5V. When the voltage from BST to SW drops

below 2.5V, the HS-FET is turned off using an

under-voltage lockout (UVLO) circuit, which

allows the LS-FET to conduct and refresh the

charge on the BST capacitor. In PSM or DCM,

the LS-FET is forced on to refresh the BST

voltage.

Since the supply current sourced from the BST

capacitor is low, the HS-FET can remain on for

more switching cycles than are required to

refresh the capacitor, making the effective duty

cycle of the switching regulator high.

The effective duty cycle during the dropout of

the regulator is mainly influenced by the voltage

drops across the power MOSFET, inductor

resistance, low-side diode, and printed circuit

board resistance.

Internal Regulator

Most of the internal circuitry is powered on by

the 5V internal regulator. This regulator takes

the VIN input and operates in the full VIN range.

When VIN is greater than 5V, the output of the

regulator is in full regulation. When VIN is lower

than 5V, the output degrades.

For better thermal performance, connect BIAS

to an external 5V source. VCC and the internal

circuit are then powered by BIAS. Since there is

an internal diode between BIAS and the internal

circuit, float BIAS or connect BIAS to GND if not

being used.

Enable (EN) Control

EN is a digital control pin that turns the

regulator on and off. When EN is pulled below

its threshold voltage, the chip is put into the

lowest shutdown current mode. Pulling EN

above its threshold voltage turns on the part.

Do not float EN.

Frequency Programmable (FREQ)

The

MPQ9842

oscillating

frequency

programmed by either an external resistor

(RFREQ) from FREQ to ground or by a logic level

SYNC signal.

The value of RFREQ can be calculated with

Equation (1):

)

(

170000

)

(

kHz

FREQ

(1)

The chip can be synchronized to an external

clock range from 350kHz up to 2.5MHz through

FREQ/SYNC.

SYNC and PHASE

The internal oscillator frequency can also be

synchronized to an external clock ranging from

350kHz to 2.5MHz through SYNC. The external

clock should be at least 250kHz larger than the

RFREQ set frequency. Ensure that the high

amplitude of the SYNC clock is higher than

1.8V, and low amplitude is lower than 0.4V.

There is no pulse width requirement, but there

is always parasitic capacitance of the pad, so if

the pulse width is too short, a clear rising and

falling edge may not be seen due to the

parasitic capacitance. The pulse should be

longer than 100ns in application.

PHASE is used when two or more MPQ9842

devices are in parallel with the same SYNC

clock. Pulling PHASE high forces the device to

operate in-phase of the SYNC clock. Pulling

PHASE low forces the device to be 180° out-of-

phase of the SYNC clock. By setting different

voltages for PHASE, two devices can operate in

180° out-of-phase to reduce the total input

current ripple, so a smaller input bypass

capacitor can be used (see Figure 3). The

PHASE rising threshold is about 2.5V with a

400mV hysteresis.

MPQ9842GL Datasheet(PDF) 22 Page - MPS Industries, Inc.

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