MPQ9842GL datasheet(27/37 Pages) MPSIND

27 / 37 page

MPQ9842

– 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER

MPQ9842 Rev. 1.1

www.MonolithicPower.com

7/29/2022

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

a tradeoff between EMI and efficiency, a ≤20Ω

RBST is recommended.

Hot-Plug Application

In a hot-plug application, the VIN pin may turn

on and off frequently before the power supply

can establish a connection with the IC. In

applications where the input power turns on and

off frequently, the BST capacitor may have a

residual voltage when the IC turns on. This may

turn on the high-side MOSFET (HS-FET) for a

short time before VCC can rise sufficiently high,

which can cause an unexpected overshoot on

VOUT.

To protect the IC, hot-plug applications are not

recommended. If a hot-plug application must be

initiated, use a small BST capacitor (e.g. 47nF),

a large VCC capacitor (e.g. 4.

7μF), and a large

PG resistor (e.g. 1MΩ) to reduce the overshoot

risk. Contact an MPS FAE to confirm the design.

PCB Layout Guidelines (8)

Efficient PCB layout, especially for the input

capacitor

placement,

critical

for

stable

operation.

four-layer

layout

strongly

recommended

achieve

better

thermal

performance. For best results, refer to Figure 7

and follow the guidelines below.

Place symmetric input capacitors as close

to VIN and GND as possible. Recommend

to connect pin1 to GND for symmetric input

structure if in-phase not used. Pin3 and

pin10 are internally connected. Connecting

together on layout or not are both OK.

Recommend to leave pin3 floating for

shorter pin4 and pin1 trace and smaller

input hot loop.

Use a large ground plane to connect to

PGND directly.

Add vias near PGND if the bottom layer is a

ground plane.

Ensure that the high-current paths at GND

and VIN have short, direct, and wide

traces.

Place

the

ceramic

input

capacitor,

especially the small package size (0603)

input bypass capacitor, as close to VIN and

PGND

possible

minimize

high-

frequency noise.

Keep the connection of the input capacitor

and VIN as short and wide as possible.

Place the VCC capacitor as close to VCC

and GND as possible.

Route SW and BST away from sensitive

analog areas such as FB.

Place the feedback resistors close to the

chip to ensure that the trace connecting to

FB is as short as possible.

10. Use multiple vias to connect the power

planes to internal layers.

NOTE:

8) The recommended PCB layout is based on Figure 8.

Top Layer

Inner Layer 1

MPQ9842GL Datasheet(PDF) 27 Page - MPS Industries, Inc.

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