Electronic Components Datasheet Search
  English  ▼

X  

ES9018 Datasheet(PDF) 27 Page - ESS Technology,Inc

Part # ES9018
Description  Reference 32-bit Audio DAC
PDF  54 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9018 Datasheet(HTML) 27 Page - ESS Technology,Inc

Back Button ES9018 Datasheet HTML 23Page - ESS Technology,Inc ES9018 Datasheet HTML 24Page - ESS Technology,Inc ES9018 Datasheet HTML 25Page - ESS Technology,Inc ES9018 Datasheet HTML 26Page - ESS Technology,Inc ES9018 Datasheet HTML 27Page - ESS Technology,Inc ES9018 Datasheet HTML 28Page - ESS Technology,Inc ES9018 Datasheet HTML 29Page - ESS Technology,Inc ES9018 Datasheet HTML 30Page - ESS Technology,Inc ES9018 Datasheet HTML 31Page - ESS Technology,Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 27 / 54 page
background image
2.3
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
COM
27
ES9018S Product Datasheet
Register 17: MODE CONTROL 5
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
1'b0
1'b0
1'b0
1'b1
1'b1
1'b1
1'b0
1'b0
Bits
Mnemonic
Description
[7]
MONO_CH_SEL
Channel select when ALL_MONO mode is enabled.
•
1'b1: Use the right channel when ALL_MONO mode is
enabled
•
1'b0: Use the left channel when ALL_MONO mode is
enabled
[6]
OSF_BYPASS
Polarity control for DAC 7.
•
1'b0: Use the OSF filter (normal operation)
•
1'b1: Send data directly from the I2S receiver to the
IIR filter at 8x.
Note: Setting to 1 will cause the signal to bypass the FIR
filters as well as the de-emphasis… filter but will still apply to
the volume controls.
[5]
DPLL_LOCK_RST_REG
DPLL_LOCK manual override.
•
1'b0: Normal Operation
•
1'b1: Manually override the DPLL_LOCK. This will
force the Jitter Eliminator to relock the signal.
[4]
AUTO_DEEMPH
SPDIF automatic de-emphasis control.
•
1'b0: De-emphasis filter is not automatically applied
•
1'b1: De-emphasis in SPDIF mode is automatically
applied with the correct frequency if 44.1k/48k/32k are
detected in the SPDIF channel status bits.
[3]
SPDIF_AUTODETECT
Automatic SPDIF input detection control.
•
1'b0: Must manually select SPDIF input.
•
1'b1: Automatically detect SPDIF input
Note: This should only be set if I2S data will not be applied to
the pins
[2]
FIR_LENGTH
2nd stage FIR filter coefficient length control.
•
1'b1: 2nd stage FIR filter is 28 coefficients in length
•
1'b0: 2nd stage FIR filter is 27 coefficients in length
[1]
FIN_PHASE_FLIP
DPLL phase invert
•
1'b0: Do not invert the phase to the DPLL
•
1'b1: Invert the phase to the DPLL
[0]
ALL_MONO
Overall DAC true mono source enable.
•
1'b0: Normal 8 channel mode
•
1'b1: All 8 DACs are sourced from one source for true
mono.
Note: The channel to use as the source is selected by the
MONO_CH_SELECT register.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com