2.3

ES9018S Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

54

Revision History

Revision

Date

Notes

Initial

January 21, 2009

Initial version

1.0

January 23, 2009

Update Register #15 default value

Update Audio Interface Timing

Update Level Linearity Error Performance

Add details to FIR Programmable Filters and Registers sections

1.1

March 13, 2009

Add ES9012

1.2

February 11, 2010

Corrected Sample Rate Calculation formula

1.21

July 26, 2012

Update feature table

1.22

December 12, 2012

Update Analog Performance table

– Maximum PCM sampling frequency

Update I2C compatible modes

Update 5V tolerant pins. Update pinout.

Update PCM Audio Interface Diagram

1.23

April 11, 2013

Correct I2C description

1.3

July 16, 2013

Add reflow profile

1.31

September 19, 2013

Correct typos and timing diagrams

1.4

June 6, 2014

Added SABRE SOUNDTM trademark

1.5

July 15, 2014

Updated ESS’ FAX number. Added medical liabilities disclaimer.

Clarified polarity of RESET input, pin 8, on page 4.

Updated supported sampling rates. ES2012 removed.

Recommended power-up sequence, timing diagram added to page 27

1.6

July 22, 2014

Pages 23 and 24, corrected the polarity of U2 on two circuit diagrams

1.7

September 16, 2014

Updated DAC output resistance from 781.25

 to 834 ±11%

1.8

January 22, 2015

Cleaned up formatting and corrected typos.

1.9

February 18, 2015

Corrected formulae on Analog Performance table.

1.91

March 18, 2015

Removed incorrect note from cover page.

Updated ESS Technology contact information.

2.0

February 16, 2016

Added I2C interface timing table

2.1

March 16, 2016

Changed CCLK input capacitance from 20pF max. to 5pF max.

2.2

May 4, 2016

Pin 24 on the pin layout diagram was erroneously marked as pin 34

2.3

August 9, 2021

Formatting changes

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are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.