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ES9826Q Datasheet(PDF) 48 Page - ESS Technology,Inc |
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ES9826Q Datasheet(HTML) 48 Page - ESS Technology,Inc |
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48 / 88 page  ES9826 Datasheet VERSION 0.1.2 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM 48 Register 1: ADC CLOCK CONFIG1 Bits [7] [6] [5:0] Default 1'b0 1'b0 6'd3 Bits Mnemonic Description [7] RESERVED NA [6] SELECT_ADC_HALF Specifies whether to halve the SELECT_ADC_NUM divider. Can only produce half of an odd number divider, SELECT_ADC_NUM must be even. • 1'b0: Disabled (default) • 1'b1: Halve the value of SELECT_ADC_NUM + 1 [5:0] SELECT_ADC_NUM Whole number divide value + 1 for CLK_ADC (MCLK/divide_value). • 6'd3: Divide by 4 (default) • 6'dn: Divide by (N + 1) |
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