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JITTER GENERATION

LOOP TIMING MODE

LOSS OF LOCK INDICATOR

LOSS OF SIGNAL

SIGNAL DETECT

MULTIPLEXER OPERATION

DEMULTIPLEXER OPERATION

SLK2511B

SLLS763B – JANUARY 2007 – REVISED MARCH 2007

jitter is presented to the inputs. The measurement bandwidth for intrinsic jitter is 12 kHz to 20 MHz.

When LOOPTIME is high, the clock synthesizer used to serialize the transmit data is bypassed and the timing is

provided by the recovered clock. However, REFCLK is still needed for the recovery loop operation.

The SLK2511B has a lock detection circuit to monitor the integrity of the data input. When the clock recovery

loop is locked to the input serial data stream, the LOL signal goes high. If the recovered clock frequency

deviates from the reference clock frequency by more than 100 ppm, LOL goes low. If the data stream clock rate

deviates by more than 170 ppm, loss of lock occurs. If the data streams clock rate deviates more than 500 ppm

from the local reference clock, the LOL output status might be unstable. Upon power up, the LOL goes low until

the PLL is close to phase lock with the local reference clock.

The loss of signal (LOS) alarm is set high when no transitions appear in the input data path for more than 2.3

µs.

The LOS signal becomes active when the above condition occurs. If the serial inputs of the device are

ac-coupled to its source, the ac-couple capacitor needs to be big enough to maintain a signal level above the

threshold of the receiver for the 2.3

µs no transition period. Once activated, the LOS alarm pin is latched high

until the receiver detects an A1A2 pattern. The recovered clock (RXCLK) is automatically locked to the local

reference when LOS occurs. The parallel data (RXDATAx) may still be processed even when LOS is activated.

The SLK2511B has an input SIGDET pin to force the device into the loss of signal state. This pin is generally

connected to the signal detect output of the optical receiver. Depending on the optics manufacturer, this signal

can be either active high or active low. To accommodate the differences, a polarity select (PS) pin is used. For

an active low, SIGDET input sets the PS pin high. For an active high, SIGDET input sets the PS pin low. When

the PS signal pin and SIGDET are of opposite polarities, the loss of signal state is generated and the device

transmits all zeroes downstream.

The 4-bit parallel LVDS data is clocked into an input buffer by a clock derived from the synthesized clock. The

data is then clocked into a 4:1 multiplexer. The D0 bit is the most significant bit and is shifted out first in the

serial output stream.

The serial 2.5 Gbps data is clocked into a 1:4 demultiplexer by the recovered clock. The D0 bit is the first bit that

is received in time from the input serial stream. The 4-bit parallel data is then sent to the LVDS driver along with

the divided down recovered clock.

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