SP8861SLASHNASLASHHP datasheet(7/15 Pages) ZARLINK

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SP8861

Fig. 7 Data format diagrams

218 217 216 215 214 213 212 211 210 29

MSB

LSB

PHASE

DETECTOR GAIN

CONTROL

(SEE TABLE 1)

PHASE

DETECTOR

SENSE BIT

(SEE TABLE 2)

15-BIT PROGRAMMABLE COUNTER (M COUNTER)

4-BIT

PROGRAMMABLE

COUNTER

(A COUNTER)

CONTROL

LOGIC

(SEE

TABLE 3)

Fig. 7a F1 or F2 word, bit allocation with 416/17 selected

217 216 215 214 213 212 211 210 29

MSB

LSB

PHASE

DETECTOR GAIN

CONTROL

(SEE TABLE 1)

15-BIT PROGRAMMABLE COUNTER (M COUNTER)

3-BIT

PROGRAMMABLE

COUNTER

(A COUNTER)

CONTROL

LOGIC

(SEE

TABLE 3)

Fig. 7b F1 or F2 word, bit allocation with 48/9 selected

MUST BE ZERO

PD1 PD2

212 211 210 29

MSB

LSB

PHASE

DETECTOR

BISTABLE

CONTROL

(SEE TABLE 4)

13-BIT PROGRAMMABLE COUNTER (R COUNTER)

CONTROL

LOGIC

(SEE

TABLE 3)

Fig. 7c Reference word bit allocation

DUAL MODULUS

N RATIO SELECT

0 = 416/17

1 = 48/9

22 BITS

0 0

22 BITS

1 0

22 BITS

1 1

22 CLOCKS

F1 WORD

F2 WORD

REF WORD

DATA LOADS ON FALLING EDGES

DATA

DATA CLOCK

CHIP SELECT

Fig. 7d Data load sequence

PHASE

DETECTOR

SENSE BIT

(SEE TABLE 2)

SP8861/NA/HP Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc

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