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SP8861/NA/HP Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
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SP8861/NA/HP Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
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3 / 15 page  3 SP8861 tS1tCH 2V tS tCH tCL tREP 2V 2V tE LAST DATA BIT FIRST DATA BIT DATA CLOCK ENABLE tREP = 1µs min., tS = 50ns min., tCH = 50ns min., tCL = 100ns min., tE = 50ns min. Fig. 4 Typical input characteristics and input drive requirements for SP8861 Fig. 5 Data and clock timing requirements FREQUENCY (MHz) 400 350 300 250 200 150 100 50 0 0 25 500 650 750 1000 1300 1500 150 80 GUARANTEED OPERATING WINDOW 416/17 MODE GUARANTEED OPERATING WINDOW 48/9 MODE TYPICAL OVERLOAD TYPICAL SENSITIVITY |
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