P3041 Features

P3041 QorIQ Communications Processor Product Brief, Rev. 0

Freescale Semiconductor

9

3.6

e500mc Core and Cache Memory Complex

The P3041 offers four high-performance, 32-bite500mc cores based on the Power Architecture® from

Power ISA 2.06. Like previous e500 cores, each e500mc is a superscalar dual issue processor, supporting

out-of-order execution and in-order completion.

3.6.1

e500mc Features Summary

Key features of the e500mc include the following:

•

Up to 1.5 GHz core clock speed

•

36 bit physical addressing

•

64 TLB SuperPages

•

512-entry, 4-Kbyte pages front-end

•

128-Kbyte backside L2 cache supporting ECC single-bit error correction

•

3 Integer units

—Two simple

— One complex (integer multiply and divide)

•

64-byte cache line

•

L1 caches, running at same frequency as CPU

— 32-Kbyte Instruction, 8 way

— 32-Kbyte Data, 8 way

— Both with data and tag parity protection

•

Supports Data Path Acceleration Architecture (DPAA) data and context “stashing” into frontside

cache

•

User, Supervisor, and Hypervisor instruction level privileges

•

New processor facilities

— Hardware support for efficient partitioning and virtualization

— Double-precision floating-point unit

– Complies with IEEE Std. 754™

– Binary-compatible with e300 and e600

– Supports 32 64-bit floating point registers for scalar single- and double-precision

floating-point arithmetic. Decorated storage facility to provide additional atomic operations

of up to two 64-bit quantities by a single access including a “fire and forget” APU for

improved statistics support

— Expanded interrupt model

– Improved programmable interrupt controller (PIC) automatically ACKs interrupts

– Implements message send and receive functions for interprocessor communication,

including receive filtering

— External PID load and store facility