WM8195 datasheet(4/33 Pages) WOLFSON

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WM8195

Production Data

PD Rev 4.1 July 2005

PIN DESCRIPTION

NAME

TYPE

DESCRIPTION

VRX

Analogue output

Input return bias voltage.

This pin must be decoupled to AGND via a capacitor.

VRLC/VBIAS

Analogue I/O

Selectable analogue output voltage for RLC or single-ended bias reference.

This pin would typically be decoupled to AGND via a capacitor.

VRLC can be externally driven if programmed Hi-Z.

AGND1

Supply

Analogue ground (0V).

BINP

Analogue input

Blue channel input video.

AGND2

Supply

Analogue ground (0V).

GINP

Analogue input

Green channel input video.

AGND3

Supply

Analogue ground (0V).

RINP

Analogue input

Red channel input video.

AGND4

Supply

Analogue ground (0V).

DVDD1

Supply

Digital supply (5V) for logic and clock generator. This must be operated at the same

potential as AVDD.

OEB

Digital input

Output Hi-Z control, all digital outputs disabled when OEB = 1.

Serial interface: enable pulse, active high

Parallel interface: strobe, active low

SEN/STB

Digital input

Latched on NRESET rising edge: if Low then device control is via serial interface,

if high then device control is via parallel interface.

SDI/DNA

Digital input

Serial interface: serial input data signal

Parallel interface:

High = data, Low = address

SCK/RNW

Digital input

Serial interface: serial clock signal

Parallel interface:

High: OP[13:6] is output bus.

Low: OP[13:6] is input bus (Hi-Z).

VSMP

Digital input

Video sample synchronisation pulse.

RLC/ACYC

Digital input

RLC (active high) selects reset level

clamp on a pixel-by-pixel basis – tie high

if used on every pixel.

ACYC autocycles between R, G, B

inputs when in Line-by-Line mode.

MCLK

Digital input

Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or

any multiple of 2 thereafter depending on input sample mode).

DGND1

Supply

Digital ground (0V).

No connection.

OP[0]

Digital output

OP[1]

Digital output

OP[2]

Digital output

Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes:

Hi-Z: when OEB = 1.

14-bit output: 14-bit data is output on OP[13:0].

8-bit multiplexed output: data is output on OP[13:6] at 2

∗ ADC conversion rate.

7-bit multiplexed output: data is output on OP[13:6] at 2

∗ ADC conversion rate.

4-bit multiplexed output: data is output on OP[13:10] at 4

∗ ADC conversion rate.

See Output Formats section in Device Description for further details.

Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0,

and SEN/STB = 0.

Output 8-bit: register read back data is output in parallel on OP[13:6] when

SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.

DVDD2

Supply

Digital I/O supply (3.3V/5V).

DGND2

Supply

Digital ground (0V).

OP[3]

Digital output

OP[4]

Digital output

OP[5]

Digital output

OP[6]

Digital I/O

See pins 21 to 23 for details.

DGND3

Supply

Digital ground (0V).

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