WM8738

Production Data

w

PD Rev 4.4 August 2006

13

AUDIO DATA SAMPLING RATES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. The external master system clock can be applied directly through the MCLK input pin.

In a system where there are a number of possible sources for the reference clock it is recommended

that the clock source with the lowest jitter be used to optimise the performance of the ADC.

The master clock for WM8738 supports audio sampling rates from 256fs to 768fs, where fs is the

audio sampling frequency LRCLK, typically 32kHz, 44.1kHz, 48kHz, or 96kHz. The master clock is

used to operate the digital filters and the noise shaping circuits.

The WM8738 has a master clock detection circuit that automatically determines the relationship

between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is

a greater than 32 clocks error the interface is disabled and maintains the output level at the last

sample. The master clock must be synchronised with LRCLK, although the WM8738 is tolerant of

phase variations or jitter on this clock. Table 1 shows the typical master clock frequency inputs for

the WM8738.

If MCLK is stopped for greater than 10us then the device will enter a low power mode where the

current taken from AVDD is greatly reduced. Note that when the device enters this mode the

references are powered down.

Table 1 shows the common MCLK frequencies for different sample rates.

Master Clock Frequency (MHz)

SAMPLING

RATE

(LRCLK)

256fs

384fs

512fs

768fs

32kHz

8.192

12.288

16.384

24.576

44.1kHz

11.2896

16.9340

22.5792

33.8688

48kHz

12.288

18.432

24.576

36.864

96kHz

24.576

36.864

Unavailable Unavailable

Table 1 Master Clock Frequency Selection