ADF4113HV

Rev. 0 | Page 13 of 20

Function Latch Map

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2

P1

000

0

CP3 CP2 CP1

0

00000

F4

F3

M3

M2

M1

F2

F1

C2(1) C1(0)

CONTROL

BITS

PRE-

SCALER

VALUE

RESERVED

CURRENT

SETTING

RESERVED

MUXOUT

CONTROL

P2

P1

PRESCALER VALUE

00

8/9

01

16/17

10

32/33

11

64/65

CPI3

CPI2

CPI1

4.7kΩ

0

0080

1

11640

F4

CHARGE PUMP

OUTPUT

0NORMAL

1

THREE-STATE

F3

PHASE DETECTOR

POLARITY

0

POSITIVE

1NEGATIVE

M3

M2

M1

OUTPUT

0

0

0

THREE-STATE OUTPUT

0

0

1

DIGITAL LOCK DETECT

(ACTIVE HIGH)

0

1

0

N DIVIDER OUTPUT

011

1

0

0

R DIVIDER OUTPUT

1

0

1

ANALOG LOCK DETECT

1

1

0

SERIAL DATA OUTPUT

1

1

1

DGND

PD1

OPERATION

0NORMAL

1POWER DOWN

F1

COUNTER

OPERATION

0NORMAL

1

R, A, B COUNTERS

HELD IN RESET

Figure 22. Function Latch Map

FUNCTION LATCH

The on-chip function latch is programmed with C2 and C1 set

to 1,0, respectively. Figure 22 shows the input data format for

programming the function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter

and the AB counters are reset. For normal operation, this bit

should be 0. Upon powering up, the F1 bit must be disabled,

and the N counter resumes counting in close alignment with

the R counter. (The maximum error is one prescaler cycle.)

Power-Down

DB3 (F2) in the function latch provides a software power-down

for the ADF4113HV. The device powers down immediately

after latching a 1 into Bit F2.

When the CE pin is low, the device immediately powers down

regardless of the state of the power-down bit (F2).

When a power-down is activated (either through software or

a CE pin activated power-down), the following events occur:

•

All active dc current paths are removed.

•

The R, N, and timeout counters are forced to their load

state conditions.

•

The charge pump is forced into three-state mode.

•

The digital clock detect circuitry is reset.

•

•

The reference input buffer circuitry is disabled.

•

The input register remains active and capable of loading

and latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on

the ADF4113HV. Figure 22 shows the truth table.

Charge Pump Currents

CPI3, CPI2, and CPI1 program the current setting for the

charge pump. The truth table is given in Figure 22.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The

prescaler value should be chosen so that the prescaler output

frequency is always less than or equal to 200 MHz. Thus, with

an RF frequency of 2 GHz, a prescaler value of 16/17 is valid,

but a value of 8/9 is not.

PD Polarity

This bit sets the phase detector polarity bit. See Figure 22.

CP Three-State

This bit controls the CP output pin. With the bit set high, the

CP output is put into three-state. With the bit set low, the CP

output is enabled.