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AD7400 Datasheet(PDF) 4 Page - Analog Devices |
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AD7400 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 20 page  AD7400 Rev. A | Page 4 of 20 TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1 Table 2. Parameter Limit at TMIN, TMAX Unit Description fMCLKOUT2 10 MHz typ Master clock output frequency 9/11 MHz min/MHz max Master clock output frequency t13 40 ns max Data access time after MCLK rising edge t23 10 ns min Data hold time after MCLK rising edge t3 0.4 × tMCLKOUT ns min Master clock low time t4 0.4 × tMCLKOUT ns min Master clock high time 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 200µA IOL 200µA IOH +1.6V TO OUTPUT PIN CL 25pF Figure 2. Load Circuit for Digital Output Timing Specifications MCLKOUT MDAT t1 t2 t4 t3 Figure 3. Data Timing |
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