LP87702 datasheet(50/99 Pages) TI

50 / 99 page

Table 8-16. BUCK1_CTRL_2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

BUCK1_SLEW_RATE

R/W

Sets the output voltage slew rate for BUCK1 converter (rising and

falling edges):

0x0 – Reserved

0x1 – Reserved

0x2 – 10 mV/μs

0x3 – 7.5 mV/μs

0x4 – 3.8 mV/μs

0x5 – 1.9 mV/μs

0x6 – 0.94 mV/μs

0x7 – 0.47 mV/μs

(Default from OTP memory)

8.6.1.1.7 BUCK0_VOUT Register (Offset = 6h) [reset = 0h]

BUCK0_VOUT is shown in Figure 8-25 and described in Table 8-17.

Return to Table 8-9.

Figure 8-25. BUCK0_VOUT Register

BUCK0_VSET

R/W-0h

Table 8-17. BUCK0_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BUCK0_VSET

R/W

Output voltage of BUCK0 converter:

0x00 ... 0x13, Reserved, DO NOT USE

0.7 V – 0.73 V, 10 mV steps

0x14 – 0.7 V

...

0x17 – 0.73 V

0.73 V – 1.4 V, 5 mV steps

0x18 – 0.735 V

...

0x9D – 1.4 V

1.4 V – 3.36 V, 20 mV steps

0x9E – 1.42 V

...

0xFF – 3.36 V

(Default from OTP memory)

8.6.1.1.8 BUCK1_VOUT Register (Offset = 7h) [reset = 0h]

BUCK1_VOUT is shown in Figure 8-26 and described in Table 8-18.

Return to Table 8-9.

Figure 8-26. BUCK1_VOUT Register

BUCK1_VSET

R/W-0h

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

www.ti.com

Submit Document Feedback

Product Folder Links: LP87702-Q1

LP87702 Datasheet(PDF) 50 Page - Texas Instruments

LP87702 Datasheet(HTML) 50 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL