ATTINY26 datasheet(21/185 Pages) ATMEL

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ATtiny26(L)

1477I–AVR–10/06

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When

the correct address is set up in the EEAR Register, the EERE bit must be set. When the

EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register.

The EEPROM read access takes one instruction and there is no need to poll the EERE

bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-

tion is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress when new data or address is written to the EEPROM I/O Registers, the

write operation will be interrupted, and the result is undefined.

Note:

1. Uses 1 MHz clock, independent of CKSEL-Fuse settings.

EEPROM Write During Power-

down Sleep Mode

When entering Power-down sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the write access time

has passed. However, when the write operation is completed, the crystal Oscillator con-

tinues running, and as a consequence, the device does not enter Power-down entirely.

It is therefore recommended to verify that the EEPROM write operation is completed

before entering Power-down.

Preventing EEPROM

Corruption

During periods of low V

CC, the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using the EEPROM, and the same design solutions

should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommen-

dations (one is sufficient):

Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the internal Brown-out Detector (BOD) if

the operating voltage matches the detection level. If not, an external Brown-out

Reset Protection circuit can be applied.

Keep the AVR core in Power-down Sleep mode during periods of low V

CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the EEPROM Registers from unintentional writes.

Store constants in Flash memory if the ability to change memory contents from software

is not required. Flash memory can not be updated by the CPU, and will not be subject to

corruption.

Table 1. EEPROM Programming Time

Symbol

Number of Calibrated RC

Oscillator Cycles(1)

Typical Programming

Time

EEPROM Write (from CPU)

8448

8.5 ms

ATTINY26 Datasheet(PDF) 21 Page - ATMEL Corporation

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