4

2487C–MICRO–03/05

AT89S51

4.

Pin Description

4.1

VCC

Supply voltage (all packages except 42-PDIP).

4.2

GND

Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the

embedded program memory).

4.3

VDD

Supply voltage for the 42-PDIP which connects only the logic core and the embedded program

memory.

4.4

PWRVDD

Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board

MUST connect both VDD and PWRVDD to the board supply voltage.

4.5

PWRGND

Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are

weakly connected through the common silicon substrate, but not through any metal link. The

application board MUST connect both GND and PWRGND to the board ground.

4.6

Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses

to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-

ing program verification. External pull-ups are required during program verification.

4.7

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin

Alternate Functions

P1.5

MOSI (used for In-System Programming)

P1.6

MISO (used for In-System Programming)

P1.7

SCK (used for In-System Programming)