ATMEGA406 datasheet(36/263 Pages) ATMEL

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2548E–AVR–07/06

ATmega406

8.6

Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-

als to reduce power consumption. The current state of the peripheral is frozen and the I/O

registers can not be written. Resources used by the peripheral when stopping the clock will

remain occupied, hence the peripheral should in most cases be disabled before stopping the

clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the

same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped.

8.6.1

PRR0 – Power Reduction Register 0

• Bit 7:4 - Res: Reserved bits

These bits are reserved in ATmega406 and will always read as zero.

• Bit 3 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When

waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 2 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 1 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 0 - PRVADC: Power Reduction V-ADC

Writing a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut

down.

Bit

7654

(0x64)

––––

PRTWI

PRTIM1

PRTIM0

PRVADC

PRR0

Read/Write

RRRR

R/W

Initial Value

0000

ATMEGA406 Datasheet(PDF) 36 Page - ATMEL Corporation

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