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ATMEGA406 Datasheet(PDF) 41 Page - ATMEL Corporation |
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ATMEGA406 Datasheet(HTML) 41 Page - ATMEL Corporation |
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41 / 263 page ![]() 41 2548E–AVR–07/06 ATmega406 Figure 9-2. Power-on Reset in Operation. 9.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 30-3 on page 230) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V RST – on its positive edge, the delay counter starts the MCU after the Time-out period – t TOUT – has expired. Figure 9-3. External Reset During Operation VBATT VCOT SLEEP_MODE POR INTERNAL_RESET Power-off Reset Active TIMEOUT tTOUT FET |
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