AT45DB642D datasheet(6/55 Pages) ATMEL

6 / 55 page

3542F–DFLASH–09/06

AT45DB642D

Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions

and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-6 on

page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit

opcode and the desired buffer or main memory address location. While the CS pin is low, tog-

gling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main memory

address location through either the SI (serial input) pin or the 8-bit input pins (I/O7 - I/O0). All

instructions, addresses, and data are transferred with the most significant bit (MSB) first.

Buffer addressing for standard DataFlash page size (1056 bytes) is referenced in the datasheet

using the terminology BFA10 - BFA0 to denote the 11 address bits required to designate a byte

address within a buffer. Main memory addressing is referenced using the terminology PA12 -

PA0 and BA10 - BA0, where PA12 - PA0 denotes the 13 address bits required to designate a

page address and BA10 - BA0 denotes the 11 address bits required to designate a byte address

within the page.

For “Power of 2” binary page size (1024 bytes) the Buffer addressing is referenced in the

datasheet using the conventional terminology BFA9 - BFA0 to denote the 10 address bits

required to designate a byte address within a buffer. Main memory addressing is referenced

using the terminology A22 - A0.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either

one of the two SRAM data buffers. The DataFlash supports RapidS and Rapid8 protocols for

Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this

datasheet for details on the clock cycle sequences for each mode.

6.1

Continuous Array Read (Legacy Command: E8H): Up to 66 MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read

command can be utilized to sequentially read a continuous stream of data from the device by

simply providing a clock signal; no additional addressing information or control signals need to

be provided. The DataFlash incorporates an internal address counter that will automatically

increment on every clock cycle, allowing one continuous read operation without the need of

additional address sequences. To perform a continuous read from the standard DataFlash page

size (1056 bytes), an opcode of E8H must be clocked into the device followed by three address

bytes (which comprise the 24-bit page and byte address sequence) and a series of don’t care

bytes (4 bytes if using the serial interface or 19 bytes if using the 8-bit interface). The first 13 bits

(PA12 - PA0) of the 24-bit address sequence specify which page of the main memory array to

read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the starting byte

address within the page. To perform a continuous read from the binary page size (1024 bytes),

the opcode (E8H) must be clocked into the device followed by three address bytes and a series

of don’t care bytes (4 bytes if using the serial interface, or 19 bytes if using the 8-bit interface).

The first 13 bits (A22 - A10) of the 24-bits sequence specify which page of the main memory

array to read, and the last 10 bits (A9 - A0) of the 24-bits address sequence specify the starting

byte address within the page. The don’t care bytes that follow the address bytes are needed to

initialize the read operation. Following the don’t care bytes, additional clock pulses on the

SCK/CLK pin will result in data being output on either the SO (serial output) pin or the eight out-

put pins (I/O7- I/O0).

AT45DB642D Datasheet(PDF) 6 Page - ATMEL Corporation

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