AT83C5121 datasheet(34/115 Pages) ATMEL

34 / 115 page

A/T8xC5121

4164G–SCR–07/06

Interrupt Generator

There are several sources of interruption but the SCIB macro-cell issues only one inter-

rupt signal: SCIB IT.

Figure 20. SCIB Interrupt Sources

This signal is high level active. One of the sources is able to set up the interrupt signal

and this is the read of the Smart Card Interrupt register by the CPU that clears this

signal.

If during the read of the Smart Card Interrupt register an interrupt occurs, the set of the

corresponding bit into the Smart Card Interrupt register and the set of the interrupt signal

will be delayed after the read access.

Registers

There are fourteen registers to control the SCIB macro-cell. They will be described in

the Section “DC/DC Converter”.

Some of the register widths are greater than a byte. Despite the 8 bits access provided

by the BIU, the address mapping of this kind of register respects the following rule:

•

The Lowest significant byte register is implemented at the higher address.

This implementation makes access to these registers easier when using high level pro-

gramming language (C,C++).

ESCTBI

CIccER

ESCWTI

ESCRI

ESCPI

ECVccER

Transmit buffer

copied to shift register

Output current

out of range

Output voltage

out of range

Timeout on WT

counter

Complete

transmission

Complete

reception

Parity error

detected

SCIB IT

ESCTI

AT83C5121 Datasheet(PDF) 34 Page - ATMEL Corporation

AT83C5121 Datasheet(HTML) 34 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL