DRA821 datasheet(2/253 Pages) TI

2 / 253 page

– Independently configurable as USB host, USB

peripheral, or USB dual-role device

Automotive interfaces:

• Twenty CAN-FD ports

• 12× Universal Asynchronous Receiver/Transmitter

(UART)

• 11× Serial Peripheral Interfaces (SPI)

• One 8-channel ADC

• 10× Inter-Integrated Circuit ( I2C™)

• 2× Improved Inter-Integrated Circuit ( I3C®)

Audio interfaces:

• 3× Multichannel Audio Serial Port (McASP)

modules

Flash memory interfaces:

• Embedded Multi Media Card ( eMMC™ 5.1)

interface

– Support speeds of up to HS400

• One Secure Digital® 3.0/Secure Digital Input

Output 3.0 (SD3.0/SDIO3.0) interfaces

• One Octal SPI / Xccela™ / HyperBus™ Memory

Controller (HBMC) interface

• 16-nm FinFET technology

• 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3

PCB

2 Applications

• Automotive gateway

• Vehicle compute

• Body control module

• Telematics control unit

• V2X/V2V

• Factory automation gateways

• Communications equipment

• Industrial transport

• Building Automation Gateway

3 Description

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems

with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through

integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-

speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3

certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller

and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing

tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a

subset of the processors and peripherals on the main domain targeted at higher functional safety enablement,

such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more

details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments

Jacinto™ 7 Family of Products (SPRUIX4).

Package Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

DRA821U4-Q1

DRA821U4

ALM (FCBGA, 433)

17.2 mm × 17.2 mm

DRA821U2-Q1

DRA821U2

ALM (FCBGA, 433)

17.2 mm × 17.2 mm

XJ7200GB

ALM (FCBGA, 433)

17.2 mm × 17.2 mm

(1)

For more information, see Mechanical, Packaging, and Orderable Information.

(2)

The package size (length × width) is a nominal value and includes pins, where applicable.

3.1 Functional Block Diagram

Figure 3-1 is functional block diagram for the device.

DRA821U-Q1, DRA821U

SPRSP57E – APRIL 2020 – REVISED JUNE 2023

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