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DAC53701 Datasheet(PDF) 32 Page - Texas Instruments |
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DAC53701 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 56 page  7.5.2.2 Command Byte Table 7-11 lists the command byte addresses. Table 7-11. Command Byte (Register Names) ADDRESS REGISTER NAME D0h STATUS D1h GENERAL_CONFIG D2h CONFIG2 D3h TRIGGER 21h DAC_DATA 25h DAC_MARGIN_HIGH 26h DAC_MARGIN_LOW 01h PMBUS_OPERATION 78h PMBUS_STATUS_BYTE 98h PMBUS_VERSION 7.5.3 I2C Read Sequence To read any register the following command sequence must be used: 1. Send a start or repeated start command with a target address and the R/ W bit set to 0 for writing. The device acknowledges this event. 2. Send a command byte for the register to be read. The device acknowledges this event again. 3. Send a repeated start with the target address and the R/ W bit set to 1 for reading. The device acknowledges this event. 4. The device writes the MSDB byte of the addressed register. The controller must acknowledge this byte. 5. Finally, the device writes out the LSDB of the register. An alternative reading method allows for reading back the value of the last register written. The sequence is a start or repeated start with the target address and the R/ W bit set to 1, and the two bytes of the last register are read out. The broadcast address cannot be used for reading. Table 7-12. Read Sequence S MSB … R/ W (0) ACK MSB … LSB ACK Sr MSB … R/ W (1) ACK MSB … LSB ACK MSB … LSB ACK Address Byte Section 7.5.2.1 Command Byte Section 7.5.2.2 Sr Address Byte Section 7.5.2.1 MSDB LSDB From controller Target From controller Target From controller Target From target Controller From target Controller DAC53701-Q1, DAC43701-Q1 SLASEW8A – OCTOBER 2020 – REVISED SEPTEMBER 2023 www.ti.com 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC53701-Q1 DAC43701-Q1 |
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