Philips Semiconductors

Product specification

FBL22033

3.3V BTL 8-bit latched/registered/pass-thru

universal transceiver with 30

Ω termination

1999 Apr 15

3

PIN CONFIGURATION

52 51 50 49 48 47 46

45 44 43 42 41 40

39

38

37

36

35

34

33

32

31

30

29

28

27

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19

20

21 22 23 24 25 26

BUS GND

B1

BUS GND

B2

BUS GND

B3

BUS GND

B4

BUS GND

B5

BUS GND

B6

BUS GND

LOGIC GND

AO1

AO2

AO3

LOOPBACK

AI4

AI5

8-Bit Universal Transceiver

FBL22033

52-lead PQFP

AI2

AI3

AO4

AI6

LOGIC GND

AO5

SG00092

DESCRIPTION

The FBL22033 is an 8-bit transceiver featuring a split input (AI) and

output (AO) bus on the TTL-level side.

The common I/O, open collector B port operates at BTL signal

levels. The logic element for data flow in each direction is controlled

by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A,

SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a

register, or a D-type latch.

When configured in the buffer mode, the inverse of the input data

appears at the output port. In the flip-flop mode, data is stored on

the rising edge of the appropriate clock input (LCAB or LCBA). In the

latch mode, clock pins serve as transparent-High latch enables.

Regardless of the mode, data is inverted from input to output.

Data flow in the B-to-A direction, regardless of the logic element

selected, is further controlled by the Loopback input. When the

Loopback input is High the output of the selected A-to-B logic

element (not inverted) becomes the B-to-A input.

The 3-State AO port is enabled by asserting a High level on OEA.

The B port has two output enables, OEB0 and OEB1. Only when

OEB0 is High and OEB1 is Low is the output enabled. When either

OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to

the level of the pull-up voltage. New data can be entered in the

flip-flop and latched modes or can be retained while the associated

outputs are in 3-State (AO port) or inactive (B port).

The B-port drivers are Low-capacitance open collectors with

controlled ramp and are designed to sink 100mA. Precision band

gap references on the B-port ensure very good noise margins by

limiting the switching threshold to a narrow region centered at 1.55V.

The B-port interfaces to “Backplane Transceiver Logic” (see the

IEEE 1194.1 BTL standard). BTL features low power consumption

by reducing voltage swing (1V p-p, between 1V and 2V) and

reduced capacitive loading by placing an internal series diode on the

drivers. BTL also provides incident wave switching, a necessity for

high performance backplanes.

Output clamps are provided on the BTL outputs to further reduce

The other clamp, the “trapped reflection” clamp, clamps out ringing

approximately 100ns after a High-to-Low transition.

To support live insertion, OEB0 is held Low during power on/off

cycles to ensure glitch- free B port drivers. Proper bias for B port

drivers during live insertion is provided by the BIAS V pin when at a

which will reverse-bias the BTL driver series Schottky diode, and

also bias the B port output pins to a voltage between 1.62V and

2.1V. This bias function is in accordance with IEEE BTL Standard

1194.1. If live insertion is not a requirement, the BIAS V pin should

The LOGIC GND and BUS GND pins are isolated inside the

package to minimize noise coupling between the BTL and TTL

sides. These pins should be tied to a common ground external to the

package.

Each BTL driver has an associated BUS GND pin that acts as a

signal return path and these BUS GND pins are internally isolated

from each other. In the event of a ground return fault, a “hard” signal

failure occurs instead of a pattern dependent error that may be very

infrequent and impossible to trouble- shoot.

As with any high power device thermal considerations are

critical. It is recommended that airflow (300Ifpm) and/or thermal

mounting be used to ensure proper junction temperature.