7.3.5 Software Reset Call

The software reset call is a command sent from the controller on the I2C bus that instructs all devices that

support the command to be reset to the power-up default state. To function as expected, the I2C bus must be

functional, and no devices can be hanging the bus.

The software reset call is defined as the following steps:

1. A start condition is sent by the I2C bus controller.

2. The address used is the reserved general call I2C bus address '0000 0000' with the R/W bit set to 0. The

byte sent is 0x00.

3. Any devices supporting the general call functionality will ACK. If the R/W bit is set to 1 (read), the device will

NACK.

4. Once the general call address is acknowledged, the controller sends only 1 byte of data equal to 0x06. If the

data byte is any other value, the device does not acknowledge or reset. If more than 1 byte is sent, no more

bytes is acknowledged, and the device ignores the I2C message considering as invalid.

5. After the 1 byte of data (0x06) is sent, the controller sends a STOP condition to end the Software Reset

sequence. A repeated START condition is ignored by the device and no reset is performed.

Once the above steps are completed successfully, the device performs a reset. This clears all register values

back to power-on defaults.

7.4 Device Functional Modes

7.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCAL9538 in a reset condition

until the supply has reached VPOR. At that time, the reset condition is released, and the TCAL9538 registers and

I2C/SMBus state machine initializes to their default states. After that, VCC must be lowered to below VPORF and

back up to the operating voltage for a power-reset cycle.

7.5 Programming

7.5.1 I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a controller sending a Start condition, a high-to-low transition

on the SDA input/output, while the SCL input is high (see Figure 7-4). After the Start condition, the device

address byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address input of the target device must not be

changed between the Start and the Stop conditions.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 7-5).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

controller (see Figure 7-4).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure

7-6). When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the

controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times

must be met for proper operation.

TCAL9538

SCPS280A – NOVEMBER 2022 – REVISED NOVEMBER 2023

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