1

0

0

A1

1

1

S

0

A

A

A

R/W

A

P

NA

S

1

MSB

LSB

MSB

LSB

Target Address

Acknowledge

From Target

Command Byte

Data From Upper

or Lower Byte

of Register

Last Byte

Data

Acknowledge

From Target

Acknowledge

From Target

Target Address

Data From Lower

or Upper Byte

of Register

First Byte

Data

No Acknowledge

From Controller

Acknowledge

From Controller

At this moment, controller transmitter

becomes controller receiver, and

target receiver becomes target transmitter.

1

0

0

1

1

R/W

Stop

Condition

A0

A1 A0

Figure 7-11. Read From Register

<br/>

SCL

SDA

INT

Start

Condition

R/W

Read From

Port

Data Into

Port

Stop

Condition

ACK From

Controller

NACK From

Controller

ACK From

Target

Data From Port

Target Address

Data From Port

1

9

R

7

6

5

4

3

2

0

1

1

S

0

1

A1

1

A

Data 1

Data 4

A

NA P

Data 2

Data 3

Data 4

Data 5

INT is cleared

by Read from Port

Stop not needed

to clear INT

tph

tps

tir

tiv

A0

A.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is

valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).

B.

This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual

data transfer from P port (see Figure 7-11).

Figure 7-12. Read Input Port Register

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TCAL9538

SCPS280A – NOVEMBER 2022 – REVISED NOVEMBER 2023

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