80C286 datasheet(30/60 Pages) INTERSIL

30 / 60 page

Bus Cycle Termination

At maximum transfer rates, the 80C286 bus alternates

between the status and command states. The bus status sig-

nals become inactive after TS so that they may correctly sig-

nal the start of the next bus operation after the completion of

the current cycle. No external indication of TC exists on the

80C286 local bus. The bus master and bus controller enter

TC directly after TS and continue executing TC cycles until

terminated by the assertion of READY.

READY Operation

The current bus master and 82C288 bus controller terminate

each bus operation simultaneously to achieve maximum bus

operation bandwidth. Both are informed in advance by

READY active (open-collector output from 82C284) which

identifies the last TC cycle of the current bus operation. The

bus master and bus controller must see the same sense of

the READY signal, thereby requiring READY to be synchro-

nous to the system clock.

Synchronous Ready

The 82C284 clock generator provides READY synchroniza-

tion from both synchronous and asynchronous sources (see

Figure 24). The synchronous ready input (SRDY) of the

clock generator is sampled with the falling edge of CLK at

the end of phase 1 of each TC. The state of SRDY is then

broadcast to the bus master and bus controller via the

READY output line.

Asynchronous Ready

Many systems have devices or subsystems that are asyn-

chronous to the system clock. As a result, their ready out-

puts cannot be guaranteed to meet the 82C284 SRDY setup

and hold time requirements. But the 82C284 asynchronous

ready input (ARDY) is designed to accept such signals. The

ARDY input is sampled at the beginning of each TC cycle by

82C284 synchronization logic. This provides one system

CLK cycle time to resolve its value before broadcasting it to

the bus master and bus controller.

ARDY or ARDYEN must be HIGH at the end of TS. ARDY

cannot be used to terminate the bus cycle with no wait

states.

Each ready input of the 82C284 has an enable pin (SRDYEN

and ARDYEN) to select whether the current bus operation

will be terminated by the synchronous or asynchronous

ready. Either of the ready inputs may terminate a bus opera-

tion. These enable inputs are active low and have the same

timing as their respective ready inputs. Address decode logic

usually selects whether the current bus operation should be

terminated by ARDY or SRDY.

FIGURE 23. CMDLY CONTROLS THE LEADING EDGE OF COMMAND SIGNAL

READ CYCLE N -1

READ CYCLE N

VALID ADDR N

VALID ADDR (N-1)

A23 - A0

PROC

CLK

• S0

ALE

READY

CMDLY

EX1

EX2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

80C286

80C286 Datasheet(PDF) 30 Page - Intersil Corporation

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