8

The interrupt status register, when read, indicates the cause

of the interrupt and resets itself on the rising edge of the RD

signal. When any of the counters having a corresponding bit

in the status register increments, that bit is set to a “1”

regardless of whether the corresponding bit in the interrupt

mask register is set or not.

Consequently, when the status register is read it will always

indicate which counters have increments and if an alarm

compare occurred, since the last time it was read. This

requires some special software considerations. If a slow

interrupt is enabled (i.e., hourly or daily), the program must

always check the slowest interrupt that has been enabled

first, because all the other lower order bits in the status

register will be set to “1” as well.

Bit D7 is the global interrupt bit, and when set to a “1”,

indicates that the ICM7170 did indeed generate a hardware

interrupt. This is useful when other interrupting devices in

addition to the ICM7170 are attached to the system

microprocessor, and all devices must be polled to determine

which one generated the interrupt.

See General Notes, Note 6.

Interrupt Operation

The Interrupt Output N-channel MOSFET (Figure 4) is enabled

whenever both the Interrupt Enable bit (D4 of the Command

Register) and a mask bit (D0 - D6 of the Interrupt Mask

Register) are set. The transistor is turned ON when a flag bit is

set that corresponds to one of the set mask bits. This also sets

the Global Interrupt Flag Bit (D7 of the Interrupt Status

Register). It is turned OFF when the Interrupt Status Register is

read. An interrupt can occur in both the operational and standby

modes of operation.

allows the Interrupt Output to turn on only while system powers

If interrupts are required only during standby operation, then the

interrupt source pin should be connected to the battery’s

the interrupt could be used to turn on power for a cold boot.

Power Down Detector

The ICM7170 contains an on-chip power down detector that

eliminates the need for external components to support the

battery-backup switchover function, as shown in Figure 6.

MOSFET), the data bus I/O buffers in the ICM7170 are

automatically disabled and the chip cannot be read or written

to. This prevents random data from the microprocessor being

written to the clock registers as the power supply is going down.

Actual switchover to battery operation occurs when the voltage

uncertainty is due to the offset voltage of the CMOS

comparator that is used to sense the battery voltage. During

battery backup, device operation is limited to timekeeping and

interrupt generation only, thus achieving micro- power current

drain. If an external battery-backup switch-over circuit is being

used with the ICM7170, or if standby battery operation is not

a 2K resistor.

D6

D5

D4

D3

D2

D1

D0

D7

INTERRUPT MASK

REGISTER

NOT

USED

PERIODIC INT’ MASK BITS

ALARM MASK BIT

INTERRUPT STATUS

REGISTER

PERIODIC INT’ FLAGS

ALARM FLAG BIT

RD OF ADD HEX 10 = >RESET

GLOBAL INTERRUPT FLAG BIT

INTERRUPT

ENABLE

COMMAND

REGISTER

BIT D4

PIN 11

PIN 12

INT

INT

SOURCE

D6

D5

D4

D3

D2

D1

D0

D7

FIGURE 5. INTERRUPT OUTPUT CIRCUIT

ICM7170