HEF4720VT datasheet(13/16 Pages) PHILIPS

13 / 16 page

January 1995

Philips Semiconductors

Product speciﬁcation

256-bit, 1-bit per word random access memories

HEF4720B

HEF4720V

Memory retention

It is sometimes necessary to ensure that the information

stored in the memory cannot be erased inadvertently. This

can be arranged by adding detection circuits, by measures

in the timing, and by the addition of a battery. With the

HEF4720B; V, memory retention is very easily obtained

because its current drain in the stand-by condition is

almost zero. The wide supply voltage range makes it

possible to keep the memory active by means of a simple

battery, thereby preventing information loss.

In designing the memory retention circuits, two aspects

should be kept in mind. The memory retention will not

function in an optimum way if the battery voltage is low or

if the voltage transitions at the address input are too slow.

The first of these is usually the result of using too simple a

battery back-up circuit, e.g. a battery charged via a diode

from the TTL supply voltage. In this case, the LOCMOS

supply voltage falls below the safe operating voltage.

Special arrangements should be made to overcome this.

Slow address transitions (the second cause of memory

loss) are due to a long RC-time in the power system. When

the power is switched on or off, the 5 V line changes

between 0 and 5 V in milliseconds to seconds so

producing a correspondingly long transition time in the

various logic outputs. This creates problems in the proper

operation of the HEF4720B; V, with loss of memory as a

possible result. This can be prevented by ensuring that

input rise and fall times do not exceed 10

µs.

Three possibilities for controlling the rise and fall times at

the HEF4720B; V interface are given here:

1. LOCMOS gates can be connected between the

address latch and the HEF4720B; V (Fig.9). In the

event of a low voltage, or mains supply failure, the

gates can be blocked by a signal from the memory

retention logic thus isolating the HEF4720B; V from

the address and CS inputs.

2. The interface power supply can be separated from the

TTL power supply by means of a low-value resistor

(Fig.10); a thyristor is connected from the interface

power supply to earth. The system is arranged so that,

upon switching off or failure of the interface supply, the

thyristor turns on thus ensuring a rapid fall of the

supply voltage.

3. The best solution is to select the interface circuits from

the LOCMOS family and to feed all these circuits from

the battery (Fig.11). These stages then remain active

when the TTL 5 V supply fails. The interface circuits

are mostly only active on a clock pulse, have the

possibility of being inactive on a gate level, or can be

forced into one position.

HEF4720VT Datasheet(PDF) 13 Page - NXP Semiconductors

HEF4720VT Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL