4724 datasheet(2/7 Pages) PHILIPS

2 / 7 page

January 1995

Philips Semiconductors

Product speciﬁcation

8-bit addressable latch

HEF4724B

MSI

DESCRIPTION

The HEF4724B is an 8-bit addressable latch with three

address inputs (A0 to A2), a data input (D), an active LOW

enable input (E), an active HIGH clear input (CL), and eight

parallel latch outputs (O0 to O7).

When E and CL are HIGH, all outputs (O0 to O7) are LOW.

Eight-channel demultiplexing or active HIGH 1-of-8

decoding with output enable operation occurs when CL is

HIGH and E is LOW. When CL and E are LOW, the

selected output (O0 to O7; determined by A0 to A2) follows

D. When E goes HIGH, the contents of the latch are

stored. When operating in the addressable latch mode

(E = CL = LOW), changing more than one bit of A0 to

A2 could impose a transient wrong address. Therefore,

this should only be done while in the memory mode

(E = HIGH, CL = LOW).

Fig.1 Functional diagram.

PINNING

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

HEF4724BP(N):

16-lead DIL; plastic

(SOT38-1)

HEF4724BD(F):

16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4724BT(D):

16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

A0 to A2

address inputs

data input

enable input (active LOW)

clear input (active HIGH)

O0 to O7

parallel latch outputs

Fig.2 Pinning diagram.

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