January 1995

4

Philips Semiconductors

Product specification

Universal timer module

HEF4753B

LSI

FUNCTIONAL DESCRIPTION

Clock divider and decoder

The clock signal at input CP is, at its original frequency, the

system clock, but it also drives the programmable counter.

The counter input frequency can be predivided by the

factors 1/16, 1/256 and 1/4096, depending on the logic

state of inputs W and X (according to the function tables

above).

8-bit programmable counter

The 8 inputs A to H are the set inputs of the 8 counter

flip-flops. The setting is triggered by an edge of the input

signal (at input IN) depending on of the chosen mode.

Event flip-flops, synchronization and edge-detection

The event flip-flops are used to recognize the positive

and/or negative edge of the input signal at IN.

Parts of the flip-flops are used together with the

programmable 8-bit counter as a retriggerable mono-flop,

which defines the time scaling for event recognition.

The input IN is synchronized by the clock signal CP.

Mode switch and output multiplexer

This function switches the chosen output to the output

(OUT) and gives the mode of which the edge at input IN

has to be detected. The inputs Z, Y and LFC give 7 modes

+1, that means in mode ‘Digital Filter’ the input LFC can be

HIGH or LOW.

OPERATING MODES

The circuit has 6 operating modes which are activated by

the logic state of inputs LFC, Y and Z. An extra mode is

possible by using two circuits which are connected such so

they function as a digital band-filter.

1. Counter mode (LFC = LOW; Y = LOW; Z = HIGH)

In this mode the output OUT should be connected to input

IN. If not, only one counter cycle starts after a transition at

input IN (see Fig.3 and note 1.).

Fig.3

A

B

C

D

E

F

G

H

W

X

LFC

Y

Z

HH

L

H

H

H

H

H

L

L

L

L

H