THERMAL METRIC(1)

TPS62830xRZE

TPS62830xDRL

UNIT

8 pin-WQFN

8 pin-SOT583

JEDEC

EVM

JEDEC

EVM

ψJB

Junction-to-board characterization parameter

30.7

44.7

22.1

28.2

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.

(2)

Not applicable to an EVM.

7.5 Electrical Characteristics

TJ = –40°C to +125°C, VIN = 2.25 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

IQ

Operating quiescent current

EN = VIN, IOUT = 0 mA, VOUT = 1.8

V, MODE = GND, device not switching

7

17

µA

ISD

VIN shutdown supply current

EN = low, TJ = -40 oC to 85 oC

100

700

nA

VUVLO(+)

Rising UVLO threshold voltage (VIN)

2.05

2.15

2.25

V

VUVLO(hys)

UVLO hysteresis (VIN)

90

120

mV

THERMAL SHUTDOWN

TJ(SD)

Thermal shutdown threshold

TJ rising

150

°C

TJ(HYS)

Thermal shutdown hysteresis

20

°C

LOGIC PINs

VEN(+)

High-level input voltage (EN)

0.8

V

VEN(-)

Low-level input voltage (EN)

0.35

V

VMODE(+)

High-level input voltage (MODE)

0.8

V

VMODE(-)

Low-level input voltage (MODE)

0.35

V

IEN(LKG)

EN Input leakage current

VEN = HIGH

10

100

nA

IMODE(LKG)

MODE Input leakage current

VMODE = HIGH

10

100

nA

STARTUP

tSS

Internal fixed soft-start time

From VOUT= 0 to VOUT= 95%

180

300

440

µs

td(EN)

Enable delay time

From EN HIGH to device starts switching

120

220

µs

REFERENCE VOLTAGE

VFB

Feedback voltage accuracy

PWM mode

495

500

505

mV

VFB

Feedback voltage accuracy

PWM mode

–1

+1

%

VFB

Feedback voltage accuracy

PFM mode, COUT,eff ≥ 15 µF, L = 0.47µH

–1

+2

%

IFB(LKG)

FB input leakage current, adjustable version VFB = 0.5 V

10

70

nA

IVOS(LKG)

VOS input leakage current

VEN = low

100

500

nA

POWER GOOD

VPG,UV(+)

Rising power good threshold

voltage (output undervoltage)

Power Good low, VFB rising

94

96

98

%

VPG,UV(-)

Falling power good threshold

voltage (output undervoltage)

Power Good high, VFB falling

90

92

94

%

VPG,OV(+)

Rising power good threshold

voltage (output overvoltage)

Power Good high, VFB rising

108

110

112

%

VPG,OV(-)

Falling power good threshold

voltage (output overvoltage)

Power Good low, VFB falling

102.5

105

107

%

td(PG)

Power good delay at start up

Low-to-high transition on the PG pin at start

up

128

µs

td(PG)

Power good deglitch delay during operation

High-to-low or low-to-high transition on the

PG pin

30

45

60

µs

IPG(LKG)

PG pin Leakage current when open drain

output is high

VPG = 5.0 V

10

100

nA

VPG,OL

PG pin low-level output voltage

IPG = 1 mA

0.4

V

POWER STAGE

RDSON(HS)

High-side MOSFET on-resistance

VIN ≥ 5 V

35

57

mΩ

RDSON(LS)

Low-side MOSFET on-resistance

VIN ≥ 5 V

18

29

mΩ

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TPS628301, TPS628302, TPS628303, TPS628304

SLVSG98A – FEBRUARY 2023 – REVISED OCTOBER 2023

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