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OPA892 Datasheet(PDF) 21 Page - Texas Instruments |
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OPA892 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 24 page ![]() 7.4.2 Layout Example R4 49.9 R5 49.9 V IN– C1 0.1 F R F 220 –15 V + – 15 V C2 6.8 F OPA892 C3 0.1 μF NULL NULL C4 0.1 μF V O V IN+ R G 22 R3 49.9 Place bypass capacitors in low ESR packages close to power pin as possible. Use multiple VIAs to connect to power plane. Remove GND and power plane near input and output pins to reduce parasitic capacitance. 7 6 8 2 3 1 NULL IN– NULL VCC+ OUT IN+ 4 VCC– 5 NC Place RF and RG resistors as close to the device pins to minimize parasitics Figure 7-8. Layout Recommendations www.ti.com OPA892 SLOSEB4 – NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: OPA892 |
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