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OPA863ADBVR Datasheet(PDF) 25 Page - Texas Instruments |
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OPA863ADBVR Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 35 page ![]() 8.4.2 Layout Example Place bypass capacitors close to power pins Place gain and feedback resistors close to pins to minimize stray capacitance Place series output resistors close to output pin to minimize parasitic capacitance Ground and power plane removed from inner layers. Ground fill on outer layers also removed Ground and power plane exist on inner layers Place bypass capacitors close to power pins Remove GND and Power plane under output and inverting pins to minimize stray PCB capacitance CBYP RF RG + – VS CBYP VS+ Representative schematic of a single channel 1 10 2 9 3 8 4 7 RS CBYP CBYP RF RF RG RG RS RS 6 5 Power Pad Figure 8-4. Layout Recommendation for Dual-Channel DSN Package www.ti.com OPA863A, OPA2863A SBOSA95D – MAY 2022 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: OPA863A OPA2863A |
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