LPC47M10X datasheet(32/188 Pages) SMSC

32 / 188 page

Page 32

STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the

command just executed.

Table 12 - Status Register 0

BIT NO.

SYMBOL

NAME

DESCRIPTION

7,6

Interrupt Code 00 - Normal termination of command. The specified

command was properly executed and completed without

error.

01 - Abnormal termination of command.

Command

execution was started, but was not successfully

completed.

10 - Invalid command. The requested command could

not be executed.

11 - Abnormal termination caused by Polling.

Seek End

The FDC completed a Seek, Relative Seek or

Recalibrate command (used during a Sense Interrupt

Command).

Equipment

Check

The TRK0 pin failed to become a "1" after:

1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to

step outward beyond Track 0.

Unused. This bit is always "0".

Head Address The current head address.

1,0

DS1,0

Drive Select

The current selected drive.

Table 13 - Status Register 1

BIT NO.

SYMBOL

NAME

DESCRIPTION

End of

Cylinder

The FDC tried to access a sector beyond the final sector

of the track (255D). Will be set if TC is not issued after

Read or Write Data command.

Unused. This bit is always "0".

Data Error

The FDC detected a CRC error in either the ID field or

the data field of a sector.

Overrun/

Underrun

Becomes set if the FDC does not receive CPU or DMA

service within the required time interval, resulting in data

overrun or underrun.

Unused. This bit is always "0".

No Data

Any one of the following:

1. Read Data, Read Deleted Data command - the FDC

did not find the specified sector.

2. Read ID command - the FDC cannot read the ID field

without an error.

3. Read A Track command - the FDC cannot find the

proper sector sequence.

Not Writeable

WP pin became a "1" while the FDC is executing a Write

Data, Write Deleted Data, or Format A Track command.

Missing

Address Mark

Any one of the following:

1. The FDC did not detect an ID address mark at the

specified track after encountering the index pulse

from the nINDEX pin twice.

The FDC cannot detect a data address mark or a

deleted data address mark on the specified track.

LPC47M10X Datasheet(PDF) 32 Page - SMSC Corporation

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